128k x 8 static ram cy7c1019b cy7c10191b cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05026 rev. *b revised october 6, 2005 features ?high speed ?t aa = 10, 12, 15 ns ? cmos for optimum speed/power ? center power/ground pinout ? automatic power-down when deselected ? easy memory expansion with ce and oe options ? functionally equivalent to cy7c1019 functional description the cy7c1019b/10191b is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. this device has an automatic power-d own feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1019b/10191b is available in standard 32-pin tsop type ii and 400-mil-wide soj packages. customers should use part number cy7c10191b when ordering parts with 10 ns t aa , and cy7c1019b when ordering 12 and 15 ns t aa . 14 15 logic block diagram pin configurations a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512 x 256 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soj 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce i/o 0 i/o 1 v cc a 13 a 16 a 15 oe i/o 7 i/o 6 a 12 a 11 a 10 a 9 i/o 2 a 0 a 4 a 5 a 6 i/o 4 v cc i/o 5 a 8 i/o 3 we v ss a 14 v ss / tsopii
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [1] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c10191b-10 7c1019b-12 7c1019b-15 unit maximum access time 10 12 15 ns maximum operating current 150 140 130 ma maximum standby current 10 10 10 ma l ? 1 1 ma operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 10% industrial ?40c to +85c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c10191b-10 7c1019b-12 7c1019b-15 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ?5 +5 ?5 +5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 150 140 130 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 40 ma l202020 i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 10 10 ma l ? 11 capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 6pf c out output capacitance 8 pf notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. tested initially and after any design or process changes that may affect these parameters.
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 3 of 8 ac test loads and waveforms switching characteristics [4] over the operating range parameter description 7c10191b-10 7c1019b-12 7c1019b-15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 10 12 15 ns t doe oe low to data valid 5 6 7 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z [5, 6] 567ns t lzce ce low to low z [6] 333ns t hzce ce high to high z [5, 6] 567ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 10 12 15 ns write cycle [7, 8] t wc write cycle time 10 12 15 ns t sce ce low to write end 8 9 10 ns t aw address set-up to write end 7 8 10 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 7 8 10 ns t sd data set-up to write end 5 6 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [6] 333ns t hzwe we low to high z [5, 6] 567ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set- up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 3 ns 3 ns output r1 480 r1 480 r2 255 r2 255 167 equivalent to: thvenin equivalent 1.73v
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 4 of 8 data retention characteristics over the operating range (l version only) parameter description conditions min. max. unit v dr v cc for data retention no input may exceed v cc + 0.5v v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 2.0 v i ccdr data retention current 300 a t cdr [3] chip deselect to data retention time 0 ns t r operation recovery time 200 s data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [9, 10] read cycle no. 2 (oe controlled) [10, 11] notes: 9. device is continuously selected. oe , ce = v il . 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce icc isb impedance address data out v cc supply current
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 5 of 8 write cycle no. 1 (ce controlled) [12, 13] write cycle no. 2 (we controlled, oe high during write) [12, 13] notes: 12. data i/o is high impedance if oe = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 14. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 14
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 6 of 8 write cycle no. 3 (we controlled, oe low) [13] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 14 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power-down standby (i sb ) x x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 12 cy7c1019b-12vc v33 32-lead 400-mil molded soj commercial cy7c1019b-12zc zs32 32-lead tsop type ii cy7c1019b-12zxc zs32 32-lead tsop type ii (pb -free ) 15 cy7c1019b-15vc v33 32-lead 400-mil molded soj commercial cy7c1019b-15vi v33 32-lead 400-mil molded soj industrial cy7c1019b-15zc zs32 32-lead tsop type ii commercial CY7C1019B-15ZXC zs32 32-lead tsop type ii (pb -free) cy7c1019b-15zi zs32 32-lead tsop type ii industrial please contact local sales represent ative regarding availability of parts
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 7 of 8 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product or company names mentioned in this document may be the trademarks of their respective holders. package diagrams 51-85033-a 51-85033-*b 32-lead (400-mil) molded soj v33 51-85095-** 32-lead tsop ii zs32
cy7c1019b cy7c10191b document #: 38-05026 rev. *b page 8 of 8 document history page document title: cy7c1019b/cy7c10191b 128k x 8 static ram document number: 38-05026 rev. ecn no. issue date orig. of change description of change ** 109949 09/25/01 szv change from spec number: 38-01115 to 38-05026 *a 116170 08/14/02 hgk 1. soj (400-mil) package outline replacing incorrect soj package 2. pin for pin compatible with cy7c1019 3. industrial packages added to ordering information *b 397875 see ecn nxr changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? updated the ordering information table on page # 6.
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